In general, a dynamic type semiconductor memory device is arranged to have a memory cell array located at a central zone of a semiconductor chip and peripheral circuits such as, for example, a data input/output buffer circuit and an address buffer/decoder circuit formed in a peripheral zone of the semiconductor chip. The dynamic type semiconductor memory device thus arranged is responsive to address signals accompanied by some control signals to preserve or retrieve data informations into or from the memory cell array. In these operations, the peripheral circuits are activated to assist the memory cell array accompanied by a plurality of sense amplifier circuits, so that electric charges discharged from the peripheral circuits flows into the semiconductor chip during those operations. On the other hand, the data informations are preserved in the form of electric charges, then the data informations are liable to be affected by the electric charges discharged from the peripheral circuits. In a serious situation, some of the data informations are inverted in logic level.
The minimum device dimension has been reduced on the basis of recent research and development efforts, and, accordingly, the amount of charges accumulated in each memory cell is decreased with the minimization of the device size. Then, the problem of inversion is more crucial. One of the solutions is to provide additional memory cells along the peripheral circuits. The additional memory cells are coupled to a pair of bit lines and the bit lines are directly supplied from a source of voltage. This means that the potential on the bit line pair coupled to the additional memory cells tends to be different from the bit line pair coupled to the memory cells of the memory cell array.
However, another problem is encountered in the proposed dynamic type semiconductor memory device in operation of the sense amplifier circuits. In detail, the minimization of the device size results in reduction of a distance between the neighboring bit line pairs. Then, a bit line pair is capacitively coupled to the neighboring bit line pairs, so that each of the bit line pair tends to be influenced by the neighboring bit line pairs, especially, the potentials on the neighboring bit line pairs. Under the influence of the neighboring bit line pairs, the sense amplifier circuits are also affected by the potentials on the neighboring bit line pairs. As a result, if a bit line pair does not neighbor the bit line pair coupled to the additional memory cells, the sense amplifier circuit is not under the influence of the difference between the neighboring bit line pairs. On the other hand, if a bit line pair neighbors the bit line pair coupled to the additional memory cells, the sense amplifier circuit operates with a characteristic different from that of the sense amplifier circuit which is free from the influence of the different potential.